1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, the present invention relates to a static random access memory (SRAM).
This application is a counterpart of Japanese application Serial Number 210729/1997, filed Aug. 5, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
The SRAM is classified as a volatile memory because it relies on the application of continuous power to maintain the stored data. If the power is interrupted, the memory contents are destroyed unless a back-up battery storage system is maintained. The SRAM output width ranges from 1 to 32 bits. Standard inputs and outputs include interfacing with CMOS, TTL, and ECL interface circuits. Power supply range includes standard 5 V and new 3.3 V standard for battery-powered applications. A SRAM is a matrix of static, volatile memory cells, and address decoding functions integrated on-chip to allow access to each cell for read/write functions. The semiconductor memory cells use active element feedback in the form of cross-coupled invertors to store a bit of information as a logic one or zero state. The active elements in a memory cell need a constant source of dc(or static) power to remain latched in the desired state. The memory cells are arranged in parallel so that all the data can be received or retrieved simultaneously.